import sys
sys.path.append("D:\\Users\\zhangjinshuai\\Desktop\\verilog_parse-master\\verilog_parse\\version_py3\\instanceBuilder")

from port_parse.port_parse import portParse
ref_file = "..\\instanceBuilder\\port_parse\\a.v"
ref_module = "a"

diff_file = "..\\instanceBuilder\\port_parse\\a.v"
diff_module = "a"

def portInfodiff(a,b):
    for i in range(3):
        if i==0:
            if(a[i]!=b[i]):
                return 1
        else:
            if(len(a[i])!=len(b[i])):
                return 1
            else:
                for j in range(len(a[i])):
                    if(a[i][j][1]!=b[i][j][1] or a[i][j][0]!=b[i][j][0]):
                       return 1
    return 0


def get_ports(file,module):
    pp =  portParse(1)

    with open(file,"r") as f:
        cont = f.read()
        pp.run(cont,module)

    return pp.portsInfo

ref_ports  = get_ports(ref_file,ref_module)
diff_ports = get_ports(diff_file,diff_module)

for p in ref_ports:
    if p not in diff_ports:
        print("+  "+p)
    else:
        if portInfodiff(ref_ports[p],diff_ports[p])==1:
            print("*  "+p)

for p in diff_ports:
    if p not in ref_ports:
        print("-  "+p)



